The present invention relates to a transistor for use in high voltage, high speed switching applications. More specifically, the present application relates to a merged gate transistor that is useful for high voltage, high speed applications.
FIG. 1 illustrates a schematic representation of a conventional field effect transistor (FET) 1. The FET 1 includes a drain D, a source S and a gate G to control current flow between the drain and the source. When FETs, like FET 1 in FIG. 1 are used in used in large switching applications, for example, in DC-DC power converters, low gate charge/capacitance and low gate-drain capacitance are important parameters in providing high frequency and high efficiency. Large drain-source voltage (Vds) swings during switching create a large “Miller effect” and as a result, excessive switching losses.
In addition, high dV/dt changes at the drain (D) may result in a voltage transient VG1 at the gate (G). The magnitude of the transient VG1 is proportional to the ratio of the gate-drain capacitance (Cgd) to the gate-source capacitance (Cgs) Cgd/Cgs. As a result, the transient VG1 may turn the transistor 1 ON briefly when not desired. This unwanted period of conduction may result in rather large power and efficiency losses. These problems are common in all FET devices whether they are silicon, non-silicon or IEMT devices.
Accordingly, it would be desirable to provide a transistor suitable for use in high voltage, high speed switching applications that avoids the problems discussed above.